![Smile :)](./images/smilies/icon_smile.gif)
I have finished the new master code will try it all this morning. We have a couple of extra Alarms now to help identify trouble spots. When commands are sent there are two possible alarms.
1) A serial data timeout, opps something has gone wrong with the comms
![Shocked :shock:](./images/smilies/icon_eek.gif)
2) Command recd does not match command sent! oh bugger now we are in a mess
![Laughing :lol:](./images/smilies/icon_lol.gif)
The Master now waits for the one second pulses from Gregs watchdog chip at the end of the main loop. It also has a fail safe in that if no 1S pulse is recd in a reasonable time then it triggers an alarm.
So the master and watchdog chips are in effect now spying on each other
![Cool 8)](./images/smilies/icon_cool.gif)
I have also made a minor change to the slave software, just increased the serial timeout to 10 seconds. it is not critical and you should only update if you have fresh slaves that need changing. It gives us a longer on balancing time > 5S possibility later on.
I may well hack on an auto off transistor to allow master to turn itself off once charging complete as well. So a momentary button to turn on master then turns transistor on. Master turns off transistor once charge completed ok. Might use pin 10 on left hand side as an output for that.
The master is now getting a bit messy and I'll have to rewrite it as some stage. All good fun though.
![Very Happy :D](./images/smilies/icon_biggrin.gif)